Helping High-Performance Computers Multi-task

“Our aim was to find a mechanism to help CPUs coordinate work between hardware, network interface cards, and hardware accelerators to optimize performance and minimize ever growing energy costs,” said Amy Ousterhout, an assistant professor in computer science at UC San Diego and a lead author on the paper.  

The researchers expect their novel contributions to be adopted by CPU manufacturers, including Intel, with a broad-reaching impact on data centers and cloud computing.

Multi-Tasking at a New Level

According to Tal Garfinkel, a UC San Diego researcher and co-author of the study, modern CPUs regularly do two things at once: computing with the data they have on hand and coordinating events from other hardware devices. These events could be simple, such as a task update from a hardware accelerator, or more involved, like receiving data from a network interface. 

CPUs in data center and cloud systems are inundated with millions of such events per second.  Each time one occurs the CPU is notified through one of two methods: “interrupts” or “polling.” 

“With interrupts, the processor immediately stops what it was doing and responds to the event, losing all its in-flight work. With polling, the processor is constantly checking to see if something has happened, wasting a lot of time,” said Garfinkel. 

While polling has become the dominant approach in high performance systems today, both existing methods exact costly overhead on the CPU. “Interrupts” can be quite expensive as hundreds of tasks could be disrupted at once by a new event, and “polling” prevents the CPU from doing useful work or going into sleep mode to conserve energy.

“Our research challenges this status quo by showing how interrupts can eliminate inefficiency, while offering the performance of polling,” said Garfinkel.

Fast and Flexible Notification

Ousterhout explained the team’s alternative to current methods.

“Extended user interrupts, or xUI, is a set of processor extensions that builds on existing models of user interrupts for enhanced performance and flexibility,” she said.

The work introduces four novel enhancements to user interrupts: tracked interrupts, hardware safepoints, a kernel bypass timer, and interrupt forwarding. These additions offer operating systems the needed support to coordinate activities more efficiently.

“The key insight of our paper changes what transpires when an interrupt arrives. The processor doesn’t need to immediately stop and throw away the work it was doing; instead it can treat this new event as just another set of instructions to carry out in parallel with all its other tasks,” said Garfinkel.

xUI accelerates interrupts, making them fast enough that the CPU can switch tasks and handle unpredictable workflows without falling back on polling or wasting CPU cores. 

Other members of the research team include Linsong Guo and Danial Zuberi, PhD students from UC San Diego, along with PhD student Berk Aydogmus and Assistant Professor Kazem Taram (PhD ’22), both from Purdue University.

The award-winning paper, Extended User Interrupts (xUI): Fast and Flexible Notification without Polling, was supported by funding from Cisco, Intel, and Google. 

The 2024 ASPLOS best paper award went to PDIP: Priority Directed Instruction Prefetching, with UC San Diego’s Dean Tullsen and Sankara Prasad Ramesh (MS ’23) on the team along with researchers with Princeton University and Intel. 

In 2023, the ASPLOS best paper award went to Going beyond the Limits of SFI: Flexible and Secure Hardware-Assisted In-Process Isolation with HFI authored by UC San Diego’s Shravan Narayan, Joey Rudek, Tal Garfinkel, Dean Tullsen and Deian Stefan and collaborators from Fastly, Rivos and Intel Labs.

Organized by the Association for Computing Machinery (ACM), ASPLOS is the premier forum for interdisciplinary systems research, spanning the boundaries of computer architecture, hardware, programming languages, compilers, operating systems, networking, and emerging technologies and applications.